1. Field of the Invention
The present invention relates to a solid-state imaging device and a method of driving the device, particularly to an amplifier type solid-state imaging device in which a source follower amplifier is disposed in a pixel section, and a method of driving the device of that type.
2. Related Background Art
FIG. 13 is a schematic diagram of a conventional solid-state imaging device, and specifically, a linear sensor including four pixels is illustrated. Reference numeral 1 (1-1 to 1-4) denotes photoelectric conversion elements such as photodiodes, 2 (2-1 to 2-4) denotes reset MOS transistors, 3 (3-1 to 3-4) denotes input MOS transistors of source followers, and 4 (4-1 to 4-4) denotes constant current sources of the source follower. The input MOS transistors 3 (3-1 to 3-4) and the constant current sources 4 (4-1 to 4-4) of the source followers are combined to form source follower amplifiers 5 (5-1 to 5-4). In FIG. 13, the source follower amplifiers using PMOS is illustrated as an example. Reference numeral 6 (6-1 to 6-4) denotes first signal transfer transistors, 7 (7-1 to 7-4) denotes holding capacitors (capacitance is hereinafter referred to as Ct), 8 denotes a scanning circuit, 9 (9-1 to 9-4) denotes second signal transfer transistors driven by a signal from the scanning circuit, 10 denotes a common output line connected in common to one end of each of the second signal transfer transistors 9, and 11 denotes an operation amplifier which forms an output amplifier. The common output line 10 is connected to one of input terminals of the operation amplifier 11. Reference numeral 12 denotes a reference voltage source connected to another input terminal of the operation amplifier 11, 13 denotes a feedback capacitor of the amplifier (capacity value is hereinafter referred to as Cf), and 14 denotes a switch for bringing the operation amplifier 11 into a buffer state. Reference numeral 15 denotes a reset power supply for resetting one end of the photoelectric conversion element 1 via the reset MOS transistor 2. Reference numeral 16 denotes an output terminal of the operation amplifier 11. An example of the solid-state imaging device having this circuit constitution is described, for example, in Japanese Patent Application No. 2002-330258 or the like.
FIG. 14 shows an operation timing chart showing an operation of the above-described circuit. The operation of the present circuit will be briefly described with reference to the drawing.
In FIG. 14, PRES denotes a reset pulse which is input into a gate of the reset MOS transistor 2, PT denotes a transfer pulse to be input into a gate of the first signal transfer transistor 6, PSR1 to PSR4 denote scanning pulses successively output from the scanning circuit 8 to drive the second signal transfer transistor 9, and PRES2 denotes a pulse to be input into the switch 14.
First, the reset MOS transistor 2 is turned on by the reset pulse PRES to reset the photoelectric conversion element 1 to a voltage determined by the reset power supply 15. After turning off the reset MOS transistor 2, the photoelectric conversion element 1 enters an accumulation operation of a light signal to produce a signal charge in accordance with a quantity of incident light. The produced signal charge is converted to a signal voltage by a capacitance which exists in a portion (not shown) connected to the photoelectric conversion element 1 and the input MOS transistor 3. The capacitance generally corresponds to a junction capacitance of the photodiode, a drain junction capacitance of the reset MOS transistor, a gate capacitance of the input MOS transistor, a capacitance between wirings or the like. However, a capacitor element may be sometimes intentionally added. After elapse of an accumulation time, the signal voltage is amplified by the source follower amplifier 5, and the amplified signal is read out into the holding capacitor 7 by turning on the first signal transfer transistor 6 by PT. It is here assumed that the signal voltage read out into the holding capacitor 7 is Vct. Next, PRES2 is turned on. When this pulse is turned on, the operation amplifier 11 functions as a buffer amplifier, and the common output line 10 is reset to a voltage determined by the reference voltage source 12. Here, the voltage is assumed as Vref1. Next, when the second signal transfer transistor 9-1 is turned on by the scanning pulse PSR1, the signal stored in the holding capacitor 7-1 is read out into the common output line 10. A voltage represented by the following equation appears at an output end of the operation amplifier 11 in accordance with the read signal.Vout=−(Ct/Cf)·(Vct−Vref1)+Vref1,where Vout denotes an output terminal voltage of the operation amplifier 11 in a period during which the scanning pulse PSR1 is turned on.
Subsequently, as shown in FIG. 14, the scanning pulses PSR2 to PSR4 and PRES2 are successively turned on to continuously read the signals of the four-pixel linear sensor. In this circuit constitution, since a gain is determined by a capacitance ratio of the feedback capacitor 13 of an amplifier section to the signal holding capacitor 7, the scanning circuit 8 may be driven so that, for example, the signals are simultaneously read from two holding capacitors, thereby attaining double gain.
A relation between the input voltage and the output voltage of the operation amplifier 11 is schematically shown in FIG. 15. Assuming that the ordinate indicates an input voltage (Vct) or an output voltage (Vout) of the operation amplifier, and the abscissa indicates values of the capacitances Ct and Cf, as shown, Vout obtained with respect to certain Vct can be schematically represented by a seesaw using Vref1 as a supporting point. A ratio of length of the seesaw corresponds to a ratio of Ct to Cf. To facilitate description, it is assumed in FIG. 15 that Vct=Vref1, when the sensor is in a dark state. At this time, in the photoelectric conversion element of FIG. 13 in which an anode is connected to the input terminal of the source follower, a terminal voltage of the photodiode rises toward a power supply side from a ground side in accordance with the quantity of received light. As a result, the signal read onto the holding capacitor Ct indicates a voltage higher than the voltage (Vref1) in the dark state. As a result, the output of the amplifier has a voltage Vref1 in the dark state, and has a voltage lower than Vref1, when the light is received (e.g., Japanese Patent Application Laid-Open No. 2002-330258).
In the source follower circuit 5 shown in FIG. 13, the gate of the input MOS transistor 3 constitutes the input terminal, and the source constitutes the output terminal. An offset voltage determined by a threshold voltage, mobility, gate length, gate width or the like of the input MOS transistor 3 is produced between the input terminal voltage and the output terminal voltage. The threshold voltage, mobility, gate length, and gate width of the MOS transistor change depending on condition variation of a manufacturing process, and therefore the offset voltage inevitably varies by the variation of the manufacturing process. When the offset voltage changes from an initially-set value, the voltage on the holding capacitor 7 also deviates from the set value. This is shown in a schematic diagram of FIG. 16. To facilitate the description, in FIG. 16, the capacitance ratio and voltage are assumed as follows.
Capacitance ratio (Ct/Cf)=1.5
Voltage at dark time (before variation)=1 V
Reference voltage=1 V
Considering the above-described conditions,Vout=−1.5×(1-1)+1=1 V,but in case that the voltage on the holding capacitor Ct deviates from 1 V to 1.2 V,Vout=−1.5×(1.2−1)+1=0.7 V.
A variation of −0.3 V is caused in an amplifier output. Supposing that the voltage on Ct at a light irradiation time is 1.6 V, then Vout=0.1 V. However, assuming that the voltage at the dark time shifts by 0.2 V as described above, the voltage on Ct at the light irradiation time also shifts to 1.8 V in parallel. Eventually, Vout<0 V is provided. Therefore, a rate is limited to a ground voltage or an output-possible lower limit value of an amplifier output, and thus a normal output is not obtained. As a result, there occurs a problem that a saturation voltage drops or that linearity of the signal is impaired. When the voltage on Ct shifts on a ground side, the voltage at the dark time is Vout, the rate is limited to a power voltage or an output-possible upper limit value of the amplifier output. This similarly results in that the normal output is not obtained, so that there occurs a problem that the signal linearity is impaired.